1. Technical Field
The present disclosure presents a computer-aided-design (CAD) tool that is capable of estimating the voltage across the gate oxide of a MOS (metal oxide semiconductor) transistor exposed to plasma during semiconductor integrated-circuit (IC) manufacturing process. Given the internal and external conditions applying to the transistor located inside the IC, the tool simulates and evaluates the plasma induced charging effect to the transistor during a plasma-based IC manufacturing process. These internal and external conditions include transistor internal physical features, transistor external configuration and connectivity, parameters related to transistor front-end process manufacturing the transistors, and parameters related to transistor back-end plasma involved process during interconnect patterning.
The disclosed tool here will be essential for equipment vendors developing charging-minimized plasma related semiconductor manufacturing equipment and process in order to achieve high manufacturability and yield for IC products. The tool will also help device engineers improve transistor design, internally and externally, to attain more accurate and relaxed plasma-charging metal (or interconnect) design rules for circuit design. It helps process engineers fine tune process recipes for minimizing plasma charging damages in transistor gate oxides as well.
2. Description of Related Art
Plasma process induced charging damages in gate oxide of transistors has long been a reliability concern in semiconductor industry. Such damage sometimes can cause failure in an entire product line during manufacturing process, incurring significant operating loss for business. The plasma charging phenomena are rather complicated because of involvement of many factors. For example, although the conditions of the plasma sources can obviously inflict the damage to transistor gate oxides, the process parameters and the internal and external physical features of the transistor itself can cause gate oxide damages as well in some cases even during a normal operating condition of a plasma source.
Though the problems have seen some alleviation in recent process technology nodes employing thinner gate oxides, they continue to exist persistently. Such concern is more obvious and serious in particular for semiconductor foundries which run an array of different process nodes from the very old 0.35 μm to the very advanced sub-20 nm process. The wide span of the process nodes here requires the use of a broad range of gate oxide thickness including a range between 35 to 60 Å which, over the years during process technology development for silicon MOSFET transistors, has seen the most devastating plasma charging induced transistor degradation.
In the past several decades, it seems that there was not much synergy between the plasma-process equipment vendors, the foundries, and the individual semiconductor manufacturers in looking into the plasma charging related issues with a more comprehensive and systematic approach. The equipment vendors tackling such issues are probably lack of more adequate information on transistors under development by the foundries and the individual semiconductor manufacturers due to the latter being reluctant to give out proprietary transistor development information. On the other hand, the foundries and the individual semiconductor manufacturers, through tremendous efforts, must learn and perfect their knowledge in the characteristics of the plasma process equipments they acquired and then fine tune performance of the plasma equipments such that the transistors they made in their IC chips suffer less damages in their gate oxides. Such an approach in the industry has been extremely expensive due to the implementation and experimentation of the test devices in the manufacturing environment. The culprit of such situation may be attributed to the lack of an inexpensive means of understanding completely and providing solutions to this decade-long industry reliability problem. A simulation and evaluation computer-aided-design tool can offer a good solution to this. However, the tool must incorporate comprehensive physical models governing the plasma charging behaviors of the transistor. It has to be capable of accurately estimating the voltage across the transistor gate oxide under any internal and external process and device conditions of the transistor exposed to the plasma sources